• DocumentCode
    3522663
  • Title

    UNified Instruction/Translation/Data (UNITD) coherence: One protocol to rule them all

  • Author

    Romanescu, Bogdan F. ; Lebeck, Alvin R. ; Sorin, Daniel J. ; Bracy, Anne

  • Author_Institution
    Duke Univ., Durham, NC, USA
  • fYear
    2010
  • fDate
    9-14 Jan. 2010
  • Firstpage
    1
  • Lastpage
    12
  • Abstract
    We propose UNITD, a unified hardware coherence framework that integrates translation coherence into the existing cache coherence protocol. In UNITD coherence protocols, the TLBs participate in the cache coherence protocol just like the instruction and data caches, without requiring any changes to the existing coherence protocol. UNITD eliminates the need for the software TLB shootdown routine, a procedure known to be performance costly and non-scalable. We evaluate snooping and directory UNITD coherence protocols on multicore processors with 2-16 cores, and we demonstrate that UNITD reduces the performance penalty associated with TLB coherence to almost zero.
  • Keywords
    cache storage; multiprocessing systems; UNITD coherence protocol; cache coherence protocol; multicore processor; unified hardware coherence framework; unified instruction-translation-data; Computer architecture; Hardware; Local activities; Memory management; Microarchitecture; Multicore processing; Multiprocessing systems; Protocols; Software maintenance; Software performance;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Performance Computer Architecture (HPCA), 2010 IEEE 16th International Symposium on
  • Conference_Location
    Bangalore
  • ISSN
    1530-0897
  • Print_ISBN
    978-1-4244-5658-1
  • Type

    conf

  • DOI
    10.1109/HPCA.2010.5416643
  • Filename
    5416643