DocumentCode
3522905
Title
LeadOut: Composing low-overhead frequency-enhancing techniques for single-thread performance in configurable multicores
Author
Greskamp, Brian ; Karpuzcu, Ulya R. ; Torrellas, Josep
Author_Institution
Dept. of Comput. Sci., Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA
fYear
2010
fDate
9-14 Jan. 2010
Firstpage
1
Lastpage
12
Abstract
Despite the ubiquity of multicores, it is as important as ever to deliver high single-thread performance. An appealing way to accomplish this is by shutting down the idle cores in the chip and running the busy, performance-critical core(s) at higher-than-nominal frequencies. To enable such frequencies, two low-overhead approaches either boost voltage beyond nominal values, or pair cores in leader-checker configurations and let them run beyond safe frequency margins. We observe that, in a large multicore with varying numbers of busy cores, individual application of either of these two techniques is suboptimal. Each alone is often unable to bring the multicore all the way to its power or temperature envelopes due to limitations in supply voltage or error rate. Moreover, we show that the two techniques are complementary, and can be synergistically combined to unlock much higher levels of single-thread performance. Finally, we demonstrate a dynamic controller that optimizes the two techniques. Our data shows that, given a 16-core multi-core where half of the cores are already busy, an additional, performance-critical thread now attains 34% higher performance than before, while consuming 220% more power.
Keywords
microprocessor chips; multiprocessing systems; optimisation; performance evaluation; boost voltage; configurable multicores; higher than nominal frequencies; leader checker configuration; low-overhead frequency-enhancing techniques; optimization; performance critical core; performance critical thread; safe frequency margins; single thread performance; supply voltage; Computer science; Dynamic voltage scaling; Error analysis; Frequency domain analysis; Hardware; Microarchitecture; Multicore processing; Temperature; Timing; Yarn;
fLanguage
English
Publisher
ieee
Conference_Titel
High Performance Computer Architecture (HPCA), 2010 IEEE 16th International Symposium on
Conference_Location
Bangalore
ISSN
1530-0897
Print_ISBN
978-1-4244-5658-1
Type
conf
DOI
10.1109/HPCA.2010.5416656
Filename
5416656
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