Multi-parallel Architecture for MD5 Implementations on FPGA with Gigabit-level Throughput

Multi-parallel architecture for MD5 (Message-Digest Algorithm 5) implemented on FPGA (Field-Programmable Gate Array) is presented in this paper. To accelerate the speed, a general architecture for Host Computer and FPGAs is proposed. The MD5 implementation is presented. Besides the internal parallelization of MD5 modules, FPGAs can be easily duplicated and connected to Ethernet LAN. The design was implemented on Cyclone II EP2C35F672C6. For a single board, a throughput of 4.3 Gbps was achieved with 30,134 logic elements and 12 concurrent MD5 modules, and 13.0 Gbps was recorded with 3 parallel FPGAs. The performance is higher compared to other recently published works.