DocumentCode :
3525359
Title :
Hybrid analytical-statistical modeling for efficiently exploring architecture and workload design spaces
Author :
Eeckhout, Lieven ; De Bosschere, Koen
Author_Institution :
Dept. of Electron. & Inf. Syst. (ELIS), Ghent Univ., Belgium
fYear :
2001
fDate :
2001
Firstpage :
25
Lastpage :
34
Abstract :
Microprocessor design time and effort are getting impractical due to the huge number of simulations that need to be done to evaluate various processor configurations for various workloads. An early design stage methodology could be useful to efficiently cull huge design spaces to identify regions of interest to be further explored using more accurate simulations. The authors present an early design stage method that bridges the gap between analytical and statistical modeling. The hybrid analytical-statistical method presented is based on the observation that register traffic characteristics exhibit power law properties which allows its to fully characterize a workload with just a few parameters which is much more efficient than the collection of distributions that need to be specified in classical statistical modeling. We evaluate the applicability and the usefulness of this hybrid analytical-statistical modeling technique to efficiently and accurately cull huge architectural design spaces. In addition, we demonstrate that this hybrid analytical-statistical modeling technique can be used to explore the entire workload space by varying just a few workload parameters
Keywords :
computer architecture; microcomputers; performance evaluation; probability; statistical analysis; virtual machines; analytical modeling; design space culling; early design stage methodology; efficient architecture exploration; hybrid analytical-statistical modeling; microprocessor design time; power law properties; processor configurations; regions of interest; register traffic characteristics; statistical modeling; workload design spaces; workload parameters; Bridges; Design methodology; Electronic mail; Electronic switching systems; Information analysis; Information systems; Microprocessors; Performance analysis; Space exploration; Traffic control;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel Architectures and Compilation Techniques, 2001. Proceedings. 2001 International Conference on
Conference_Location :
Barcelona
ISSN :
1089-796X
Print_ISBN :
0-7695-1363-8
Type :
conf
DOI :
10.1109/PACT.2001.953285
Filename :
953285
Link To Document :
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