Pixel readout ASIC with per pixel digitization and digital storage for the DSSC detector at XFEL

The DSSC collaboration is developing an instrument for the detection of synchrotron X-rays (E >; 0.5 keV) at XFEL. The hexagonal pixels of a DEPFET based sensor with integrated signal compression will be read out by bump-bonded pixel readout ASICs. Each ASIC will have 64 × 64 pixel channels of 236 × 204 μm² area, each one containing a low-noise (<; 50 e^-) amplification of the DEPFET signal, an 8 bit single-slope ADC and a digital memory, as well as other blocks for test injection, gain switching and trimming. Data is acquired during the XFEL burst at a rate of up to 4.5 MHz. The signal is first processed by a trapezoidal shaping filter, digitized immediately and then stored to the in-pixel memory of >; 512 events capacity. The accumulated digital data is transferred off chip during the 100 ms long burst gaps on a single serial link while the analogue sections are shut down to bring the average power dissipation to <; 100 mW per ASIC. The chip architecture is described and results obtained from first test chips are presented.