A 20ps resolution wave union FPGA TDC with on-chip real time correction

Benefit from wave union, the bins (especially the ultra-wide bins) are sub-divided by each other, making FPGA TDC achieve a resolution beyond its cell delay. At such high level resolution, delay chain becomes very sensitive to the environment disturbance, including power supply voltage, temperature and current surge. On chip calibration needs lots of events and hence cannot follow fast delay changes of the chain. On-chip real time correction method proposed in this article gives one correcting parameter for each sample, making the FPGA TDC stronger when exposed to fast disturbance. A fast encoding logic is also implemented in our design and the dead time can be reduced to 1 clock cycle in the best case. Test results show a typical RMS of 20ps and the max RMS is below 30ps.