Fine-grained analysis and design of ASIP instruction set for application of encryption

Focusing on the defects of application-specific integrated processor (ASIP) design for encryption including complexity, long-term of development and lack of compatibility, in this paper we present an ASIP design method based on reconfigurable embedded RISC processor core, taking advantage of novel fine-grained code analysis technology. This relatively concise design process includes taking fine-grained analysis of target encryption code, extending instructions of the critical parts, and coupling the extended instructions as a co-processor in hardware structure with a general main-processor. As an instance, we take secure hash algorithm (SHA) as the target code, design and implement an ASIP in this process. The hardware verification and implementation result signifies that the designed processor has, at expense of relatively small chip area consumed, achieved obvious increase of performance for encryption.