High-speed hardware algorithms for Chinese remainder theorem

A residue number system (RNS) is one of the candidates for high-speed digital signal processing, because of its parallelism property with carry-free operation. However, RNS possesses a drawback that it requires time-consuming extra modules, binary to residue (B/R) and residue to binary (R/B) converters. To realize the R/B converter, the Chinese remainder theorem (CRT) are often employed. In hardware realization, the CRT can be reduced to multi-operand modular addition, which has usually been realized as several stages of carry propagate adder (CPA). In this paper, high-speed hardware algorithms for the CRT are proposed. We can reduce a number of CPA stage to one with carry save adders (CSA), and two methods, speed or size intensive versions are shown