• DocumentCode
    3527048
  • Title

    Graphical FPGA design for a predictive controller with application to spacecraft rendezvous

  • Author

    Hartley, Edward N. ; Maciejowski, Jan M.

  • Author_Institution
    Univ. of Cambridge, Cambridge, UK
  • fYear
    2013
  • fDate
    10-13 Dec. 2013
  • Firstpage
    1971
  • Lastpage
    1976
  • Abstract
    A reconfigurable field-programmable gate array (FPGA)-based predictive controller based on Nesterov´s fast gradient method is designed using Simulink and converted to VHDL using Mathworks´ HDL Coder. The implementation is verified by application to a spacecraft rendezvous and capture scenario, with communication between the FPGA and a simulation of the relative dynamics occuring over Ethernet. For a problem with 120 decision variables and 240 constraints, computation times of 0.95 ms are achieved with a clock rate of 50 MHz, corresponding to a speed up of more than 2000 over running the algorithm directly on a MicroBlaze microprocessor implemented on the same FPGA.
  • Keywords
    aerospace control; control engineering computing; field programmable gate arrays; hardware description languages; local area networks; microprocessor chips; predictive control; space vehicles; Ethernet; Mathworks HDL Coder; MicroBlaze microprocessor; Nesterov fast gradient method; Simulink; VHDL; field programmable gate array; graphical FPGA design; predictive controller; spacecraft capture scenario; spacecraft rendezvous; very high scale description language; Clocks; Delays; Field programmable gate arrays; Hardware design languages; Random access memory; Software packages; Vectors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Decision and Control (CDC), 2013 IEEE 52nd Annual Conference on
  • Conference_Location
    Firenze
  • ISSN
    0743-1546
  • Print_ISBN
    978-1-4673-5714-2
  • Type

    conf

  • DOI
    10.1109/CDC.2013.6760170
  • Filename
    6760170