Implementing narrow-band FIR filters using FPGAs

Author

Dick, Chris H. ; Harris, Fred

Author_Institution

Sch. of Electron. Eng., La Trobe Univ., Melbourne, Vic., Australia

Volume

2

fYear

1996

fDate

12-15 May 1996

Firstpage

289

Abstract

This paper addresses the problem of implementing narrow-band FIR filters using FPGAs. A method based on re-quantization of the input data stream using a sigma-delta modulator is presented. The reduced bit length representation of the re-quantized input samples removes the requirement for a full multiplier in the filter hardware. The filtering technique is described and implementation results using a Xilinx XC4010 FPGA are presented. Using a bit-serial approach, a 200 tap narrow-band filter operating at a sample rate of 1.56 MHz has been developed

Keywords

FIR filters; digital filters; encoding; field programmable gate arrays; modulators; sigma-delta modulation; 1.56 MHz; FIR filters; FPGA; Xilinx XC4010 FPGA; bit-serial approach; filter hardware; filtering; input data stream; multiplier; narrow-band filter; reduced bit length representation; requantization; sample rate; sigma-delta modulator; Arithmetic; Bandwidth; Delta-sigma modulation; Dynamic range; Encoding; Field programmable gate arrays; Filtering; Finite impulse response filter; Hardware; Narrowband;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on

Conference_Location

Atlanta, GA

Print_ISBN

0-7803-3073-0

Type

conf

DOI

10.1109/ISCAS.1996.541703

Filename

541703