• DocumentCode
    3527595
  • Title

    Time-triggered communication scheduling analysis for real-time multicore systems

  • Author

    Freier, Matthias ; Jian-Jia Chen

  • Author_Institution
    Corp. Sector Res. Renningen, Robert Bosch GmbH, Renningen, Germany
  • fYear
    2015
  • fDate
    8-10 June 2015
  • Firstpage
    1
  • Lastpage
    9
  • Abstract
    The demand for more computing power in current real-time systems carries on the development and research on multicore devices. Especially for hard real-time applications, like an engine control system, the software needs to be distributed and scheduled effectively. These applications consist of many tasks, which communicate data among each other. Considering a multicore system, communication between cores may require a lot of time. A bus architecture becomes a communication bottleneck with an increasing number of cores. Therefore, we consider a scalable communication structure like a Network-on-Chip (NoC). This paper studies the schedulability analysis of tangled tasks by resolving the communication dependencies with a Time-Triggered Constant Phase (TTCP) scheduler. A TTCP scheduler assigns periodic time slots for each computation and each communication entity. With the TTCP approach, we can highly utilize the NoC and the cores considering a tangled task model. However, this approach requires a method getting a feasible set of these time slots. We provide a schedulability analysis and a heuristic algorithm, that runs in pseudo-polynomial time complexity, for assigning the time slots. Experiments confirm this result and show the effectiveness of our heuristic algorithm for assigning the time slots for our approach. For typical industrial task sets with 1000 tasks, our approach can utilize the NoC by around 60%, while holding all real-time constraints.
  • Keywords
    computational complexity; multiprocessing systems; network-on-chip; processor scheduling; real-time systems; NoC; TTCP scheduler; bus architecture; communication bottleneck; communication dependencies; communication entity; computing power; hard real-time applications; heuristic algorithm; multicore devices; network-on-chip; periodic time slots; pseudopolynomial time complexity; real-time constraints; real-time multicore systems; scalable communication structure; schedulability analysis; tangled task model; time-triggered communication scheduling analysis; time-triggered constant phase scheduler; Algorithm design and analysis; Delays; Multicore processing; Processor scheduling; Real-time systems; Schedules; Switches;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Industrial Embedded Systems (SIES), 2015 10th IEEE International Symposium on
  • Conference_Location
    Siegen
  • Type

    conf

  • DOI
    10.1109/SIES.2015.7185046
  • Filename
    7185046