Realizable reduction of RLC circuits using node elimination

Reduction of an extracted netlist is an important step in the design and analysis of VLSI circuits. This paper describes a method for realizable reduction of extracted RLC netlists by node elimination. The proposed method eliminates nodes with time constants below a user specified time constant. By giving the freedom to the user to select a critical point in the spectrum of nodal time constants, this method provides an option to make a trade off between accuracy and reduction. The proposed method preserves the dc characteristics and the first two moments at all nodes. It also recognizes and eliminates all the redundant inductances generated by the extraction tools. The proposed method naturally reduces to TICER in the absence of any inductances.