Backward-annotation of post-layout delay information into high-level synthesis process for performance optimization

This paper presents a method of incorporating physical layout aspects into high-level synthesis (HLS) process for performance optimization. First we extract accurate interconnection delay from a layout design obtained after placement and routing and back-annotate the extracted delay to the control/data flow graph (CDFG). Then we run HLS again on the back-annotated CDFG in order to improve the performance of the synthesized design. The re-synthesis does not alter the datapath but may alter the control unit and the clock period. The experimental results show that the proposed method is effective in improving the performance of the synthesized design