Design of Fault Tolerant Arithmetic & Logical Unit Using Reversible Logic

In VLSI designs today, the device dimensions are shrinking and the circuit complexity is also growing exponentially. This device scaling leads to power dissipation, demanding for better power optimizations methods. Also when output is generated in conventional logic circuits the input vector gets lost. Losing information in a circuit causes losing power. The gate/circuit that does not loose information is called reversible gate. Energy dissipation would not occur, if a computation is done in a reversible way. In this paper, the basic concepts of reversible circuits are briefly discussed. Furthermore, an efficient & low cost fault tolerant reversible Arithmetic and logical unit (ALU) is designed and implemented. The results are then compared with the existing design. The large garbage outputs in the proposed design are compensated by the number of operations that it can perform. The Proposed design can perform almost all arithmetic and logical operations on the other hand existing design performs only four operations.