Design and Implementation of 8-Bit Vedic Multiplier Using CMOS Logic

A multiplier is a vital element in almost all the processors and contributes significantly to the total power utilization of the system. The novel point is the efficient use of Vedic algorithm (sutras) that reduces the number of computational steps considerably compared with any conventional method. The schematic for this multiplier is designed using Tanner Tool. The design is then verified in T-SPICE using 180 nm CMOS technology model library file. The analysis is made for voltage ranges of 2.5V to 5V, to simulate the design. A CMOS multiplier, with low power consumption and high linearity is proposed. The results prove that the proposed multiplier consumes 75% less power compared to the gate level analysis done earlier. The core area of the proposed multiplier is 720 um2. Paper presents a methodical design methodology for this improved performance digital multiplier based on Vedic mathematics.