Design guideline for CMOS drivers with considerations of simultaneous switching noise

Author

Han, Sung-Woo ; Kwon, Oh-Kyong

Author_Institution

Div. of Electron. & Electr. Eng., Hanyang Univ., Seoul, South Korea

fYear

1999

fDate

1999

Firstpage

45

Lastpage

48

Abstract

This paper describes a design guideline for CMOS drivers considering the simultaneous switching noise (SSN) on the power bus. This guideline employs two practical design parameters: the gate propagation delay of the active (or switching) drivers and the noise on the outputs of the quiet drivers. From the SSN model including the quiet drivers, the formulas for these design parameters are derived and used for constructing our design guideline. A safe area satisfying the given constraints on the design parameters is obtained as a function of the MOSFET channel width and the effective inductance of the power bus. The proposed formulas for design parameters and the design guideline for the drivers are confirmed through HSPICE simulation using a level 28 MOSFET model of a 0.35 μm CMOS process

Keywords

CMOS analogue integrated circuits; SPICE; circuit simulation; delays; driver circuits; inductance; integrated circuit design; integrated circuit noise; 0.35 mum; CMOS drivers; HSPICE simulation; MOSFET channel width; active drivers; design guideline; design parameters; effective inductance; gate propagation delay; level 28 MOSFET model; output noise; power bus; quiet drivers; safe area; simultaneous switching noise; Active noise reduction; Driver circuits; Guidelines; Inductance; Logic; MOSFET circuits; Noise generators; Propagation delay; Semiconductor device modeling; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI and CAD, 1999. ICVC '99. 6th International Conference on

Conference_Location

Seoul

Print_ISBN

0-7803-5727-2

Type

conf

DOI

10.1109/ICVC.1999.820817

Filename

820817