Performance Analysis and Implementation of Scalable Encryption Algorithm on FPGA

Scalable Encryption Algorithm (SEA), a parametric block cipher finds its application for confined processing resources and throughput requirement. It is an efficient solution for small embedded application and initially used for software implementation in controllers, smart card, processors and many other resources constrained systems (e.g. sensor networks RFIDs). In this paper, an algorithm is presented whose performance is investigated in recent field programmable array devices. For this purpose different modules of algorithm like encrypt block, decrypt block and key Schedule are written separately and then integrated in an iterative loop architecture thus allowing efficient combination of encryption, decryption and "on-the-fly" key derivation. The synthesis results for area utilization, working frequency and throughput are verified on target platform Virtex-5.