Design of Low Power and High Speed 4-Bit Comparator Using Transmission Gate

This paper present two different designs for 4-bit comparator, one is using CMOS technology and another is designed using Transmission Gate. Firstly we have designed various CMOS devices and generate its symbol and using this 4 bit CMOS comparator is implemented. The comparator circuit produce 3 outputs X, Y and Z. X is active when A=B, Y is active when A<;B and Z is active when A>B. Our approach to design comparator is by connecting desired symbol and design for 4-bit comparator. After that all the logic gates are designed by transmission gate and connect it to design Comparator. From the given comparison table we see that power dissipation and delay is reduced up to 65% and 50% respectively in Transmission gate comparator in Comparison with CMOS comparator. All the simulations are performed using tanner EDA software at TSMC 180 nm technology.