Dynamic Branch Prediction Modeller for RISC Architecture

In the past decade, by taking advantage of the RISC architecture, computer designers were able to benefits from the ILP and started using deeper pipelines, wider issue rates and super scalar techniques. However, due to the presence of branch instruction there is change in flow of instruction execution. In case of branch either we have to stall the pipeline until the branch instruction executes or we have to predict the branch output i.e. either branch is taken or not taken. Adding stalls in pipeline leads to the performance loss. Branch prediction is a widely referenced technique to overcome the Performance loss. It minimizes Performance loss by predicting the branch behaviour and issue subsequent instructions before the actual branch outcome is known. Whenever a prediction of branch is correct, penalty in pipeline is either reduced or completely avoided. Ironically, with shorter clock periods, the branch predictor has less time to make a prediction and might have to be scaled back to make it faster, which decreases accuracy and reduces the advantage of higher clock rates. We are going to analyze several algorithms for branch predictions in our first phase i.e. PHASE Φ. In order to support our analysis we are going to construct our own simulator for RISC architecture and putting-up some concrete results for these algorithms that can be referred for future researches.