FPGA-based digital-controlled power converter with universal input meeting 80 Plus platinum efficiency code and standby power code for sever power applications

This paper contributes to the presentation of control technique for digital-controlled power converter meeting platinum efficiency code and standby power code for sever power applications. Two control modes are presented in this paper in order to achieve standby power code. A control method to achieve constant bandwidth for power factor stage despite of input voltage variation, changing from 90V/AC to 264V/AC. Controller design and loss analysis of converter in order to achieve platinum efficiency code is included. Experimental results derived from an FPGA-based digital-controlled power converter for sever power are presented. It will be shown that the standby power is less than 0.5W and light load efficiency is improved to go up to more than 90% for both low line and high line input voltage. Moreover, it will be confirmed that the platinum efficiency code can be met under 20%, 50% and 100% load conditions. The efficiency is 91.60 %, 93.17 % and 89.66 % for low line input, respectively. The efficiency is 93.09 %, 94.51 % and 91.64 % for high line input, respectively. These results fully support the claims and contributions of this paper.