Hardware synthesis for stack type partitioned-bus architecture

Author

Kim, Kisun ; Choi, Kiyoung ; Jun, Young-Hyun

Author_Institution

RAMBUS Dev. Team, Hyundai MicroElectron., Seoul, South Korea

fYear

1999

fDate

1999

Firstpage

81

Lastpage

84

Abstract

Due to an efficient interconnect structure and internal parallelism, partitioned-bus architecture is viable for deep sub-micron chip design. In this paper, we propose a new partitioned-bus architecture and its supporting high-level synthesis methodology. The new architecture extends an existing linear architecture by stacking multiple layers for handling large datapath intensive applications. Experiments show that the approach generates compact datapath layout with flexibility of aspect ratio and reduces average bus driving length

Keywords

VLSI; circuit CAD; high level synthesis; integrated circuit design; microprocessor chips; parallel architectures; HLS methodology; aspect ratio; average bus driving length reduction; compact datapath layout; deep submicron chip design; hardware synthesis; high-level synthesis methodology; interconnect structure; internal parallelism; large datapath intensive applications; stack type partitioned-bus architecture; Circuit synthesis; Control system synthesis; Electronic mail; Hardware; High level synthesis; Integrated circuit interconnections; Microelectronics; Space technology; Stacking; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI and CAD, 1999. ICVC '99. 6th International Conference on

Conference_Location

Seoul

Print_ISBN

0-7803-5727-2

Type

conf

DOI

10.1109/ICVC.1999.820830

Filename

820830