DocumentCode
3528764
Title
New corner rounding process for sub-0.15 μm shallow trench isolation
Author
Kim, Weon-Gil ; Kim, Jong-Kook ; Kim, Choong-Bae ; Choi, Chang-Ju ; Kim, Jin-Woong ; Kim, Yil-Wook ; Choi, II-Hyun
Author_Institution
Memory Res. & Dev. Div., Hyundai Electron. Ind. Co. Ltd., Ichon, South Korea
fYear
1999
fDate
1999
Firstpage
133
Lastpage
135
Abstract
To obtain a top corner rounding in the Shallow Trench Isolation (STI) process with a hard mask, a new etching spacer and Si soft etching for an useful top corner process is evaluated. This technique utilizes the oxide rounding and, thus, effectively suppresses the inverse narrow width effect due to the stress reduction at the top corner and the less interface influence between active and field oxide. Also this technique showed no degradation of junction leakage current and less profile micro-loading effect compared with the conventional resist mask process. As a result, it has been found that this technique is very effective for sub-0.15 μm STI formation
Keywords
CMOS integrated circuits; VLSI; etching; isolation technology; silicon; 0.15 micron; CMOS technology; STI process; Si; Si soft etching; corner rounding process; etching spacer; hard mask; inverse narrow width effect suppression; junction leakage current; oxide rounding; profile micro-loading effect; shallow trench isolation; stress reduction; Electric variables; Electronics industry; Etching; Leakage current; MOSFET circuits; Polymers; Resists; Scanning electron microscopy; Stress; Transmission electron microscopy;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI and CAD, 1999. ICVC '99. 6th International Conference on
Conference_Location
Seoul
Print_ISBN
0-7803-5727-2
Type
conf
DOI
10.1109/ICVC.1999.820848
Filename
820848
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