40 nm electron beam patterning and its application to silicon nano-structure fabrication

Author

Han, Sangyeon ; Park, Taejun ; Kim, Bonkee ; Shin, Hyungcheol ; Lee, Kwyro

Author_Institution

Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea

fYear

1999

fDate

1999

Firstpage

163

Lastpage

166

Abstract

We report on 40 nm patterning using an E-beam lithography system. SAL601 negative E-beam resist was used for this experiment. In order to utilize the maximum ability of the E-beam system, we reduced the PR thickness to 100 nm, and the field size to 200 μm. In this way, PEB (Post Expose Bake) time and temperature, which are very important factors for nanopatterning, were reduced for minimum line width. In addition, digitizing was optimized for better results. Quantum wires, quantum dots, and quantum dots on a narrow channel, which can be used for nano-scale memory devices (such as single electron memory devices), were fabricated using these lithography techniques

Keywords

electron beam lithography; elemental semiconductors; nanotechnology; semiconductor quantum dots; semiconductor quantum wires; silicon; single electron transistors; 100 nm; 40 nm; 40 nm electron beam patterning; PR thickness reduction; SAL601 negative E-beam resist; Si; Si nano-structure fabrication; digitizing methods; electron beam lithography system; field size; minimum line width; nano-scale memory devices; nanopatterning; narrow channel; post expose bake time; post exposure bake temperature; quantum dots; quantum wires; single electron memory devices; Electron beams; Lithography; Nanopatterning; Nanoscale devices; Quantum dots; Resists; Silicon; Single electron memory; Temperature; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI and CAD, 1999. ICVC '99. 6th International Conference on

Conference_Location

Seoul

Print_ISBN

0-7803-5727-2

Type

conf

DOI

10.1109/ICVC.1999.820860

Filename

820860