Title :
Cost effective value prediction microarchitecture using partial-tag and narrow-width operands
Author :
Choi, Byung-Soo ; Lee, Dong-Ik
Author_Institution :
Dept. of Inf. & Commun., K-JIST, Kwangju, South Korea
Abstract :
In this paper we investigate the implementation cost of value prediction methods for high performance microprocessors and propose a new value prediction microarchitecture with low cost. After simulation, we found that the proposed microarchitecture can decrease the implementation cost by 36% to 50% and with slight performance degradation (less than 5%)
Keywords :
parallel programming; table lookup; high performance microprocessors; implementation cost; narrow-width operands; partial-tag; value prediction methods; value prediction microarchitecture; Cost function; Degradation; Equations; Laboratories; Microarchitecture; Microprocessors; Performance analysis; Performance loss; Prediction methods; Table lookup;
Conference_Titel :
Communications, Computers and signal Processing, 2001. PACRIM. 2001 IEEE Pacific Rim Conference on
Conference_Location :
Victoria, BC
Print_ISBN :
0-7803-7080-5
DOI :
10.1109/PACRIM.2001.953587
