Title :
Programmable kernel analog VLSI convolution chip for real time vision processing
Author :
Serrano-Gotarredona, T. ; Linares-Barranco, B. ; Andreou, A.G.
Author_Institution :
Inst. de Microelectron. de Sevilla, CSIC, Madrid, Spain
Abstract :
A neural architecture that implements a programmable 2D image filter has been presented. The architecture allows to implement any 2D filter F(p,q) decomposable into x-axis and y-axis components F(p,q) = H(p)V(q) such that the product can be approximated by a signed minimum. Positive and negative values of H(p) and V(q) can be programmed. The architecture requires an address even representation (AER) input. This allows to rotate the 2D convolution kernel any angle. Circuit simulation results of critical components were given. System-level behavioral simulations of a 128x128 array have been included which validate the proposed approach
Keywords :
MOS analogue integrated circuits; VLSI; analogue integrated circuits; analogue processing circuits; convolution; filters; image processing equipment; neural chips; real-time systems; 128 pixel; 16384 pixel; 2D convolution kernel rotation; AER input; address even representation input; circuit simulation; critical components; programmable 2D image filter; programmable kernel analog VLSI convolution chip; real-time vision processing; signed minimum approximation; system-level behavioral simulations; Convolution; EPROM; Filtering; Filters; Humans; Kernel; Machine vision; Neurons; Space vector pulse width modulation; Very large scale integration;
Conference_Titel :
Neural Networks, 2000. IJCNN 2000, Proceedings of the IEEE-INNS-ENNS International Joint Conference on
Conference_Location :
Como
Print_ISBN :
0-7695-0619-4
DOI :
10.1109/IJCNN.2000.860750
