Advanced interconnect technologies for ULSI scaling

Author

Kikkawa, Takamaro

Author_Institution

Res. Center for Nanodevices & Syst., Hiroshima Univ., Japan

fYear

1999

fDate

1999

Firstpage

202

Lastpage

207

Abstract

This paper describes advanced interconnect technologies with respect to ULSI scaling. Copper interconnects and low-k interlayer dielectrics, in conjunction with chemical mechanical polishing (CMP) planarization, are key technologies for future scaled ULSIs to reduce the RC delay of global interconnects. Salicide is an essential technology for sub-quarter micron CMOS gate and source/drain electrodes to reduce the parasitic resistances of transistors for high-speed logic ULSIs. Consequently, both resistivity and capacitance are key factors for materials used in the interconnect technologies for ULSI scaling

Keywords

ULSI; capacitance; chemical mechanical polishing; copper; delays; dielectric thin films; high-speed integrated circuits; integrated circuit interconnections; integrated logic circuits; CMP planarization; Cu; Cu interconnects; RC delay reduction; ULSI scaling; capacitance; chemical mechanical polishing; gate electrodes; global interconnects; high-speed logic; interconnect technologies; low-k interlayer dielectrics; parasitic resistance reduction; resistivity; salicide technology; source/drain electrodes; sub-quarter micron CMOS; CMOS logic circuits; CMOS technology; Chemical technology; Conductivity; Copper; Delay; Dielectrics; Electrodes; Planarization; Ultra large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI and CAD, 1999. ICVC '99. 6th International Conference on

Conference_Location

Seoul

Print_ISBN

0-7803-5727-2

Type

conf

DOI

10.1109/ICVC.1999.820876

Filename

820876