A pipelined row address decoding scheme for hierarchical word line structure DRAM

We propose a fast row cycle DRAM core architecture, which employs the pipelined row address decoding scheme for an hierarchical word line structure. The pipelined row address decoding scheme decreases the amount of the skew during the decoding operation. We obtain the row cycle time by reducing the latency from the beginning of the input address signal to the latching of the sub word line signal. We confirm an 9.14 ns row address cycle time at 2.5 V, even when a row address in the identical cell array is successively accessed by HSPICE simulation based on a LG 0.18 μm technology. Adding the latch circuits for pipelining, the area penalty is only 2% of the total size compared with conventional pipelined row address decoding schemes and power dissipation is about 7.5% larger