Hardware-accelerated edge detection for polarimetric synthetic aperture radar data

From the literature review, there are two constant false alarm rate detectors for detecting edges in multi-look fully polarimetric synthetic aperture radar (POLSAR) imagery, namely the likelihood ratio edge detector and the Roy´s largest eigenvalue-based edge detector. In the latter approach, one major restriction is the computation complexity, i.e. in the context of the chosen C language-based implementation. Thus, in this paper, a novel hardware-based architecture is presented to improve the processing time for the Roy´s largest eigenvalue-based edge detection. The algorithm was implemented in a field-programmable gate array (FPGA) with an accelerated solution targeting data rates of up to 1 Gb/s. Its performance was examined using nine-look NASA/JPL C-band data and evaluated in terms of processing speed and accuracy as compared to the C language-based implementation on a personal computer (PC) with a Core¿ 2 Duo processor clocked at 2.2 GHz.