Title :
FPGA based TDC using Virtex-4 ISERDES blocks
Author :
Imrek, Jozsef ; Hegyesi, Gyula ; Kalinka, G. ; Molnar, Jozsef ; Nagy, Ferenc ; Valastyan, I. ; Szabo, Zsolt
Author_Institution :
Inst. of Nucl. Res., Hungarian Acad. of Sci., Debrecen, Hungary
fDate :
Oct. 30 2010-Nov. 6 2010
Abstract :
We report on the implementation of an interleaving TDC architecture based on Virtex-4 ISERDES blocks. Multiple ISERDES blocks are used for each input channel in a split-phase arrangement. The architecture has moderate resolution (312 ps in this implementation), it is not sensitive to PVT variations, requires only limited FPGA resources, and thus suitable for high channel counts.
Keywords :
field programmable gate arrays; FPGA-based TDC; PVT variations; Virtex-4 ISERDES blocks; high channel counts; split-phase arrangement; time-to-digital converters; Calibration; Clocks; Conferences; Delay; Delay lines; Field programmable gate arrays; Protocols; FPGA; ISERDES; TDC; Virtex-4; interleaving;
Conference_Titel :
Nuclear Science Symposium Conference Record (NSS/MIC), 2010 IEEE
Conference_Location :
Knoxville, TN
Print_ISBN :
978-1-4244-9106-3
DOI :
10.1109/NSSMIC.2010.5874005
