Characterizing PLL Jitter from power supply fluctuation using mixed-signal simulations

Characterizing PLL Jitter is important yet challenging. Usually done through transistor-level transient analysis, slow simulation speed has been the major bottleneck preventing jitter from being characterized in a timely manner. This paper presents an approach for fast jitter characterization using mixed-signal simulation (combination of transistor-level blocks and calibrated behavioral models). Among various PLL jitter mechanisms, jitter from CMOS gate switching threshold variation due to power supply fluctuation is chosen to be the focus. Analog/digital converters carrying dynamic power supply dependency, together with behavioral models written in Verilog-AMS, are used to approximately model and characterize the targeted type of jitter. Jitter characterization using this method is applied to two PLL blocks, phase detector and frequency divider. Results show that jitter measured from the proposed method is in good agreement with transistor-level simulation and the speed improvement from mixed-signal simulation is significant, proving this method to be a feasible approach for fast jitter characterization.