DocumentCode :
3531024
Title :
Tutorial T7B: Optimally Addressing Verification Constraint Complexity for Effective Functional Convergence
Author :
Hemmady, S.
fYear :
2012
fDate :
7-11 Jan. 2012
Firstpage :
27
Lastpage :
27
Abstract :
As SoC design becomes larger and more complex, verification engineers are expanding constrained-random testing to meet the validation demand. This expansion creates a new set of challenges: engineers now face exponentially growing verification performance and capacity issues. It is no longer enough to write constraints that simply function to validate a design. Today, engineers must also optimize the constraints they write for performance if they wish to have any hope of both successfully validating their design and meeting their deadlines. In this tutorial, we discuss a scalable methodology for writing constraints and optimizing performance is which will improve engineers´ productivity to write and debug ever-increasing amounts of larger, more complex sets of constraints. Our goal is to reduce the time needed for functional convergence, and later for debug and volume manufacturing. We will also discuss the vital role of Verification IP providers and users in this scenario.
Keywords :
integrated circuit design; integrated circuit reliability; integrated circuit testing; system-on-chip; SoC design; capacity issues; constrained-random testing; debug; effective functional convergence; optimally addressing verification constraint complexity; scalable methodology; validation demand; verification IP providers; verification IP users; verification performance; volume manufacturing; writing constraints; Convergence; Knowledge engineering; Social network services; System-on-a-chip; Tutorials;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design (VLSID), 2012 25th International Conference on
Conference_Location :
Hyderabad
ISSN :
1063-9667
Print_ISBN :
978-1-4673-0438-2
Type :
conf
DOI :
10.1109/VLSID.2012.35
Filename :
6167716
Link To Document :
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