• DocumentCode
    3531025
  • Title

    Functional ECO automation challenges and solutions

  • Author

    Jayalakshmi, Andal

  • Author_Institution
    Intel, Bayan Lepas, Malaysia
  • fYear
    2010
  • fDate
    3-4 Aug. 2010
  • Firstpage
    126
  • Lastpage
    129
  • Abstract
    Late Register Transfer language (RTL) changes also called as Engineering Change Orders (ECOs) pose a big challenge to the design community. This is due to the reason that the ECO changes are to be made directly in the final converged netlist which differs significantly with the RTL due to optimization and convergence. Since the ECOs are done very close to tape out, these are time critical missions and any inefficiency in implementation will directly impact the cost of the product. This is the motivation behind the automation solutions that exist today for solving the functional ECO problem. A successful ECO is not only measured based on the functional equivalence with the new RTL but also on the quality of the ECO changes made. If the ECO tool inserts a lot of new logic in the converged netlist resulting in routing congestion and timing issues, it may not be possible to implement the ECO though the final netlist passes Functional Verification (FV). Thus there are a few criteria to successfully implement a functional ECO. This paper discusses the ECO challenges and reviews the criteria for a successful functional ECO solution. It also consolidates the ideas that will help to solve the issues that happen during a functional ECO.
  • Keywords
    VLSI; convergence; electronic engineering computing; formal verification; logic design; network routing; optimisation; project engineering; ECO automation challenges; converged netlist; convergence; design community; engineering change orders; functional verification; optimization; register transfer language; routing congestion; timing issues; Costs; Design automation; Design engineering; Error correction; Logic design; Routing; Signal design; Signal processing; Signal synthesis; Very large scale integration; ECO; Equivalence; Functional Verification; Logic Synthesis; Scan;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Quality Electronic Design (ASQED), 2010 2nd Asia Symposium on
  • Conference_Location
    Penang
  • Print_ISBN
    978-1-4244-7809-5
  • Type

    conf

  • DOI
    10.1109/ASQED.2010.5548226
  • Filename
    5548226