• DocumentCode
    3531107
  • Title

    Adaptive hardware context-switching approach for reconfigurable systems

  • Author

    Lee, Trong-Yen ; Tseng, Shiau-Jiun ; Hu, Che-Cheng

  • Author_Institution
    Inst. of Commun. Eng., Nat. Taipei Univ. of Technol., Taipei, Taiwan
  • fYear
    2010
  • fDate
    3-4 Aug. 2010
  • Firstpage
    140
  • Lastpage
    145
  • Abstract
    Nowadays, the ability of dynamic reconfigurable in FPGA architecture has gain its importance while switching on hardware modules. But for recent researches on reconfigurable architecture, most of them aim at one specific version. It´s inconvenient by adding additional hardware circuits to apply on all the versions. Therefore, we propose an adaptive hardware context-switching approach for reconfigurable systems. Accompany with the general bit saving format, it suits all types of Xilinx Virtex-2, Virtex-4 and Virtex-5. Which can reduces the saving number of saved frame address and bit-index. The experimental results shown that the proposed adaptive hardware context switching method reduces 60.39% in memory space and 54.47% in instruction space.
  • Keywords
    field programmable gate arrays; memory architecture; reconfigurable architectures; FPGA architecture; Virtex-4; Virtex-5; Xilinx Virtex-2; adaptive hardware context-switching approach; bit-index; dynamic reconfigurable; hardware circuits; hardware modules; instruction space; memory space; reconfigurable architecture; reconfigurable systems; Central Processing Unit; Circuits; Communication switching; Context; Field programmable gate arrays; Hardware; Reconfigurable architectures; Reconfigurable logic; Registers; Runtime; FPGA; Reconfigurable system; hardware context; readback;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Quality Electronic Design (ASQED), 2010 2nd Asia Symposium on
  • Conference_Location
    Penang
  • Print_ISBN
    978-1-4244-7809-5
  • Type

    conf

  • DOI
    10.1109/ASQED.2010.5548233
  • Filename
    5548233