Title :
Embedded Tutorial ET3: Packaging Trends, Die Package Co-Design Flow and Challenges
Author_Institution :
Texas Instrum., Bangalore, India
Abstract :
Summary form only given. Packaging has become one of the critical areas of the SoC design flow in recent years. Miniaturization of package with the ever increasing interface speeds and massive integration have opened up a lot of challenges for packaging engineers. This talk will cover different popular packages available in the industry and recent package trends. Traditionally, package design and analysis always followed SoC design, but it is becoming more and more imperative to design die and package in conjunction. Designing the die and package together in the loop to optimize die and package design and closure is popularly referred to as die package co-design. This talk will focus on the key aspects of co-design flow, package modeling/analysis aspects specifically for high performance designs. This talk will also cover some key issues and challenges from practical designs.
Keywords :
electronics packaging; network synthesis; system-on-chip; SoC design flow; die package codesign flow; massive integration; package miniaturization trend; package modeling-analysis; packaging engineer; Analytical models; Chip scale packaging; Packaging; Reliability; System-on-a-chip; Tutorials;
Conference_Titel :
VLSI Design (VLSID), 2012 25th International Conference on
Conference_Location :
Hyderabad
Print_ISBN :
978-1-4673-0438-2
DOI :
10.1109/VLSID.2012.40