Extended compatibility path based hardware binding algorithm for area-time efficient designs

Hardware binding is a crucial step in high-level synthesis. In this paper we propose a path based hardware binding algorithm to create area-time efficient designs. The algorithm performs simultaneous FU and register binding based on weighted and ordered compatibility graphs. The proposed algorithm tries to reduce interconnects in the design by exploiting flow dependencies in the DFG, leading to area reduction. The algorithm has been successfully implemented within a C to RTL framework. Experimental results on a set of commonly used benchmarks show that the proposed algorithm is able to achieve significant reductions in routing resources, area and delay when compared to the weighted bipartite matching(WBM) algorithm and the compatibility path based(CPB) binding method. In addition, when compared to WBM and CPB methods, the new algorithm has an average reduction of 29.21% & 12.49% in the area-time product respectively.