Abstract :
Summary form only given. System on Chip (SoC) design promises to revolutionize a vast array of products and markets. Access to advanced semiconductor technology is opening up new markets and facilitating innovation at a rate which we have not seen before. All of this bodes well for a vibrant semiconductor industry its associated EDA industry. Yet, there is a problem. The cost of design for SoC devices is growing at a rapid pace. Complexity is contributing to this cost rise. Because of shrinking market windows, it also becomes necessary to reuse semiconductor IP, either from third party sources or prior internal designs there is just not enough time to design much of these chips from scratch. But the quality and completeness of this IP is often not completely known, further contributing to the cost and schedule uncertainty of SoC devices. Structured design methodologies that focus on early identification and correction of design issues, rigorous methods to qualify semiconductor IP and automated approaches to assembling the components of an SoC promise to address many of the cost and schedule challenges. This early analysis methodology has been called "SoC Realization". In this panel discussion, we will explore the meaning of SoC Realization and discuss its impact on the cost and schedule for advanced SoC designs.
