DocumentCode :
3531220
Title :
Power Aware Hardware Prototyping of Multiclass SVM Classifier Through Reconfiguration
Author :
Patil, Rajesh A. ; Gupta, Gauri ; Sahula, Vineet ; Mandal, A.S.
fYear :
2012
fDate :
7-11 Jan. 2012
Firstpage :
62
Lastpage :
67
Abstract :
This paper presents power aware hardware implementation of multiclass Support Vector Machine on FPGA using systolic array architecture. It uses Partial reconfiguration schemes of XILINX for power optimal implementation of the design. Systolic array architecture provides efficient memory management, reduced complexity, and efficient data transfer mechanisms. Multiclass support vector machine is used as classifier for facial expression recognition system, which identifies one of six basic facial expressions such as smile, surprise, sad, anger, disgust, and fear. The extracted parameters from training phase of the SVM are used to implement testing phase of the SVM on the hardware. In the architecture, vector multiplication operation and classification of pair wise classifiers is designed. A data set of Cohn Kanade database in six different classes is used for training and testing of proposed SVM. This architecture is then partially reconfigured using difference based approach with the help of XILINX EDA tools. For feature classification power reduction is achieved using reconfiguration.
Keywords :
emotion recognition; face recognition; field programmable gate arrays; image classification; power aware computing; support vector machines; systolic arrays; vectors; Cohn Kanade database; FPGA; XILINX EDA tools; anger; complexity reduction; data transfer mechanisms; disgust; facial expression recognition system; fear; memory management; multiclass SVM classifier; pair wise classifier classification; parameter extraction; partial reconfiguration schemes; power aware hardware prototyping; sad; smile; surprise; systolic array architecture; vector multiplication operation; Arrays; Field programmable gate arrays; Hardware; Support vector machines; Training; Vectors; SVM; dynamic partial reconfiguration; systolic array;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design (VLSID), 2012 25th International Conference on
Conference_Location :
Hyderabad
ISSN :
1063-9667
Print_ISBN :
978-1-4673-0438-2
Type :
conf
DOI :
10.1109/VLSID.2012.47
Filename :
6167729
Link To Document :
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