DocumentCode
3531409
Title
Pole-Zero Analysis of Low-Dropout (LDO) Regulators: A Tutorial Overview
Author
Garimella, Annajirao ; Surkanti, Punith R. ; Furth, Paul M.
fYear
2012
fDate
7-11 Jan. 2012
Firstpage
131
Lastpage
136
Abstract
Analyzing poles and zeros of a circuit is often essential for (a) choose the appropriate topology for given specifications, (b) understanding the frequency response of the circuit and (c) stabilizing the circuit by choosing appropriate frequency compensation techniques. Analyzing poles and zeros of a low-dropout (LDO) voltage regulator is often intriguing as (a) the voltage/current control loop need to be broken for small signal analysis and (b) the location of poles move with output load current. The objective of this tutorial is to provide a step-by-step procedure for analyzing poles and zeros in LDO regulators. To this end, two recent state-of-the-art LDO regulators from the literature are analyzed, explaining several intricacies involved. During the process, several frequency compensation techniques are elucidated.
Keywords
Capacitors; Equations; Mathematical model; Poles and zeros; Regulators; Resistors; Transistors; Frequency compensation; LHP zero; cascode compensation; current buffers; low-dropout (LDO) voltage regulators; pole-zero analysis; power-supply rejection (PSR);
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design (VLSID), 2012 25th International Conference on
Conference_Location
Hyderabad, India
ISSN
1063-9667
Print_ISBN
978-1-4673-0438-2
Type
conf
DOI
10.1109/VLSID.2012.59
Filename
6167741
Link To Document