DocumentCode
3531533
Title
Low-Latency No-Handshake GALS Interfaces for Fast-Receiver Links
Author
Chabloz, Jean Michel ; Hemani, Ahmed
Author_Institution
KTH - R. Inst. of Technol., Stockholm, Sweden
fYear
2012
fDate
7-11 Jan. 2012
Firstpage
191
Lastpage
196
Abstract
In this paper we introduce a novel interface for Globally-Asynchronous, Locally-Synchronous systems which does not use any form of handshake to cross the gap between the clock domains. In particular, links in which the Receiver runs faster than the Transmitter are targeted. The interface works by finding an approximate ratio between the clock frequencies. Then, ratiochronous synchronizers that can tolerate clock drifts are employed to transmit data from the Transmitter to the Receiver clock domain. Thanks to the periodic properties of rationally-related systems, no handshake is employed and the average latency of the interface is decreased 75 % compared to state-of-the-art GALS interfaces. Additionally, the interface uses only standard cells and, save for a delay line, can be designed at Register Transfer Level.
Keywords
clocks; network synthesis; clock frequencies; fast-receiver links; globally-asynchronou, locally-synchronous systems; low-latency no-handshake GALS interfaces; receiver clock domain; register transfer level; Clocks; Estimation; Frequency synchronization; Jitter; Receivers; Synchronization; Transmitters; GALS; GRLS; interfaces; latency;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design (VLSID), 2012 25th International Conference on
Conference_Location
Hyderabad
ISSN
1063-9667
Print_ISBN
978-1-4673-0438-2
Type
conf
DOI
10.1109/VLSID.2012.69
Filename
6167751
Link To Document