DocumentCode
3531673
Title
Transactional WaveCache: Towards Speculative and Out-of-Order DataFlow Execution of Memory Operations
Author
Marzulo, Leandro A J ; Franca, Felipe M G ; Costa, Vítor Santos
Author_Institution
Syst. Eng. & Comput. Sci. Program, Univ. Fed. do Rio de Janeir, Rio de Janeiro
fYear
2008
fDate
Oct. 29 2008-Nov. 1 2008
Firstpage
183
Lastpage
190
Abstract
The WaveScalar is the first dataflow architecture that can efficiently provide the sequential memory semantics required by imperative languages. This work presents a speculative memory disambiguation mechanism for this architecture, the transaction WaveCache. Our mechanism maintains the execution order of memory operations within blocks of code, called waves, but adds the ability to speculatively execute, out-of-order, operations from different waves. This mechanism is inspired by progress in supporting transactional memories. Waves are considered as atomic regions and executed as nested transactions. Wave that have finished the execution of all their memory operations are committed, as soon as the previous waves are also committed. If a hazard is detected in a speculative wave, all the following waves (children) are aborted and re-executed. We evaluated the transactional WaveCache on a set of benchmarks from Spec 2000, Mediabench and Mibench (telecomm). Speedups ranging from 1.31 to 2.24 (related to the original WaveScalar) where observed when the benchmark doesn´t perform lots of emulated function calls or access memory very often. Low speedups of 1.1 to slowdowns of 0.96 were observed when the opposite happens or when the memory concurrency was high.
Keywords
data flow computing; memory architecture; Mediabench; Mibench; Spec 2000; WaveScalar; dataflow architecture; imperative languages; memory operations; out-of-order dataflow execution; sequential memory semantics; transactional WaveCache; transactional memories; Computer architecture; Computer science; Concurrent computing; Data engineering; Hardware; High performance computing; Out of order; Parallel processing; Systems engineering and theory; Telecommunications; DataFlow; Transactional Memories; WaveScalar;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Architecture and High Performance Computing, 2008. SBAC-PAD '08. 20th International Symposium on
Conference_Location
Campo Grande, MS
ISSN
1550-6533
Print_ISBN
978-0-7695-3423-7
Type
conf
DOI
10.1109/SBAC-PAD.2008.29
Filename
4685743
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