• DocumentCode
    3531683
  • Title

    Way Sharing Set Associative Cache Architecture

  • Author

    Janraj, C.J. ; Kalyan, T. Venkata ; Warrier, Tripti ; Mutyam, Madhu

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Indian Inst. of Technol. Madras, Chennai, India
  • fYear
    2012
  • fDate
    7-11 Jan. 2012
  • Firstpage
    251
  • Lastpage
    256
  • Abstract
    In order to minimize the conflict miss rate, cache memories can be organized in set-associative manner. The downside of increasing the associativity is increase in the per access energy consumption. In conventional n-way set-associative caches, irrespective of the set-wise demand, each set has n cache ways at its disposal, but cache sets may exhibit non-uniform demand for these cache ways. Exploiting this property, we propose a novel cache architecture, called way sharing cache, wherein by allowing sharing of cache ways among a pair of cache sets, we obtain dynamic energy savings as high as 41% in DL1 cache with negligible performance penalty.
  • Keywords
    cache storage; DL1 cache; cache memories; dynamic energy savings; energy consumption; n-way set-associative caches; way sharing set associative cache architecture; Art; Benchmark testing; Cache memory; Computer architecture; Energy consumption; Power demand; Shift registers; energy-efficient technique; set-associative cache;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design (VLSID), 2012 25th International Conference on
  • Conference_Location
    Hyderabad
  • ISSN
    1063-9667
  • Print_ISBN
    978-1-4673-0438-2
  • Type

    conf

  • DOI
    10.1109/VLSID.2012.79
  • Filename
    6167760