Title :
A Novel SET/SEU Hardened Parallel I/O Port
Author :
Razmkhah, Mohammad-Hamed ; Miremadi, Seyed Ghassem ; Ejlali, Alireza ; Fazeli, Mahdi
Author_Institution :
Dept. of Comput. Eng., Sharif Univ. of Technol., Tehran
Abstract :
The continuous decrease in CMOS technology feature size increases the susceptibility of such circuits to single event transient SET and single event upset SEU, caused by energetic particles striking system wires and flip flops. This paper presents a novel SET/SEU-detection technique for I/O ports where different sampling times used to detect the effects of SET/SEUs. The power dissipation, area, reliability, and propagation delay of the SET/SEU-detection I/O port are analyzed by HSPICE v.X-2005.v9 simulation. The results show that this I/O port can detect all SET/SEUs, by consumption of about 113% more power and occupation of 145% more area than simple I/O port.
Keywords :
CMOS integrated circuits; SPICE; CMOS technology; HSPICE; SET/SEU-detection; hardened parallel I/O port; single event transient; single event upset; Actuators; CMOS technology; Circuit faults; Embedded system; Phase detection; Power system reliability; Propagation delay; Sampling methods; Sensor systems; Single event upset;
Conference_Titel :
Testing and Diagnosis, 2009. ICTD 2009. IEEE Circuits and Systems International Conference on
Conference_Location :
Chengdu
Print_ISBN :
978-1-4244-2587-7
DOI :
10.1109/CAS-ICTD.2009.4960762
