Implementation and Transmission Error Handling of Multi-channel LVDS

Author

Li Xiangyang

Author_Institution

Dept. of Comput. Sci., Guangdong AIB Polytech. Coll., Guangzhou, China

fYear

2013

fDate

9-11 Sept. 2013

Firstpage

466

Lastpage

470

Abstract

Low-Voltage Differential Signaling (LVDS) evolves over the last decade to meet specific requirements such as Bus LVDS and Multipoint LVDS. This paper first presents a method to implement the multi-channel LVDS in the parallel RapidIO protocol using CPLD device and VHDL language, followed by a detailed discussion of the data line transmission error generated during the process of high-speed data transportation due to clock-data skew and difference between transmission lines. A logical component, 4-bit-channel aligner, is developed and simulated to solve this sort of transmission error. Finally, an evaluation board of RapidIO protocol is developed to evaluate the correctness of multi-channel LVDS data transmission. Some experiments show that the multi-channel LVDS is simple and strong anti-interference.

Keywords

data communication; hardware description languages; logic design; network interfaces; protocols; CPLD device; VHDL language; bus LVDS; channel aligner; clock-data skew; data line transmission error; high-speed data transportation; logical component; low-voltage differential signaling; multichannel LVDS data transmission; multipoint LVDS; parallel RapidIO protocol; strong antiinterference; transmission error handling; word length 4 bit; Clocks; Computers; Data communication; Delays; Protocols; Receivers; Synchronization; LVDS; RapidIO; channel aligner; clock-data skew;

fLanguage

English

Publisher

ieee

Conference_Titel

Emerging Intelligent Data and Web Technologies (EIDWT), 2013 Fourth International Conference on

Conference_Location

Xi´an

Print_ISBN

978-1-4799-2140-9

Type

conf

DOI

10.1109/EIDWT.2013.84

Filename

6631662