A high throughput 16 by 16 bit multiplier for DSP cores

In the rapidly growing portable telecommunications industry digital signal processing (DSP) chips are at the center of interest. The demand for higher performance for these chips continues to escalate. Coupled with demand for higher performance is the emphasis on lowering the power supply for portable electronics. Lowering the power supply has a negative impact on performance. Lowering the power supply with no degradation in performance for DSP chips requires a re-evaluation of architecture, algorithm, circuit design, and technology. Circuit style is a key factor in meeting these goals. Static CMOS has been the conventional technology of choice for some time because of its robustness and good performance. A faster circuit style such as dynamic logic is needed as power supplies go lower and performance needs increase. Dual rail domino is one type of dynamic logic that can meet these goals. Multipliers perform an essential function in DSP cores and can be heavily used depending upon the application. Depending upon the size of the operands, multipliers can occupy a significant portion of the chip area. In contrast multipliers in FPUs typically have large operands thus creating long delay paths. Hence, they are usually pipelined in order to meet performance goals. This paper focuses on a 16 by 16 array multiplier that operates at a clock frequency of 500 MHz with four cycles of latency. The multiplier is designed in dual rail domino logic using a 0.35 μm CMOS process