At-speed Testing of Asynchronous Reset De-assertion Faults

In sub-threshold technology nodes, device failure due to timing related defects (setup & hold timing) is on rise due to extreme process variability and increasing use of voltage scaling techniques for achieving required performance. High coverage using stuck-at fault patterns, which can effectively screen static defects is no longer sufficient to control DPPM (Defective parts per million). High test coverage of timing defects that is induced by process variation is required for controlling DPPM. Lot of work has been done to find the ways to increase the delay test coverage of industrial circuits including the various methods to cover inter-domain clock faults but very little or no work is done on the ways to effectively cover the asynchronous reset paths to the memory registers for timing defects. In this paper we propose a novel methodology that allows us to effectively detect the failures induced by timing defects on asynchronous reset path of the registers. This problem is further complicated by the fact that commercially available ATPG tools are not capable of generating test patterns due to modeling limitations. Results from 45nm industrial multi-million gates design is presented to illustrate the effectiveness of the proposed methodology.