Title :
Effect of gate-level design margin relaxation on overall circuit performance metrics in VLSI design
Author :
Kim, Jae Hoon ; Kim, Young Hwan
Author_Institution :
Div. of Electr. & Comput. Eng., Pohang Univ. of Sci. & Technol., Pohang, South Korea
Abstract :
This paper investigates the effects of gate-level design margin relaxation on overall circuit performance metrics, such as yield, power and area, which are sensitive to process variation. Experimental results indicate that if we design the circuit using relaxed design margin, the circuit yield is somewhat reduced, but we can get some advantages in area and power aspects compared to worst-case design. In addition to these benefits, we can gain advantages by using the deterministic design infrastructure which is widely used in modern circuit design.
Keywords :
VLSI; integrated circuit design; integrated circuit measurement; integrated circuit yield; semiconductor device measurement; VLSI design; circuit area; circuit design; circuit power; circuit yield; gate-level design margin relaxation; overall circuit performance metrics; Circuit optimization; Circuit synthesis; Delay; Design engineering; Design methodology; Performance analysis; Power engineering computing; Process design; Timing; Very large scale integration; Gate-level design margin; design resources; process variation; yield;
Conference_Titel :
Quality Electronic Design (ASQED), 2010 2nd Asia Symposium on
Conference_Location :
Penang
Print_ISBN :
978-1-4244-7809-5
DOI :
10.1109/ASQED.2010.5548316
