Effect of gate-level design margin relaxation on overall circuit performance metrics in VLSI design

This paper investigates the effects of gate-level design margin relaxation on overall circuit performance metrics, such as yield, power and area, which are sensitive to process variation. Experimental results indicate that if we design the circuit using relaxed design margin, the circuit yield is somewhat reduced, but we can get some advantages in area and power aspects compared to worst-case design. In addition to these benefits, we can gain advantages by using the deterministic design infrastructure which is widely used in modern circuit design.