BIST Approach for testing Embedded Memory Blocks in System-on-Chips

Author

Zhang, Zhiquan ; Wen, Zhiping ; Chen, Lei

Author_Institution

Beijing Microelectron. Tech.Instn. (BMTI), Beijing

fYear

2009

fDate

28-29 April 2009

Firstpage

1

Lastpage

3

Abstract

This paper presents a built-in self-test (BIST) approach to test embedded memory blocks in configurable system-on-chips (SoCs). The idea of this paper is to develop BIST architecture and BIST configurations for testing embedded memory blocks in Xilinx Virtexl-4 series SoCs by using an embedded FPGA core. The proposed approach tests RAMs operating in all of different sizes both in single-port and dual- port modes. The paper also has developed a parameterized VerilogHDL code which is portable and can be used to test embedded memories with minimal changes in any configurable SoCs.

Keywords

built-in self test; embedded systems; field programmable gate arrays; hardware description languages; integrated circuit testing; random-access storage; system-on-chip; BIST approach; BIST architecture; BIST configurations; RAM; VerilogHDL code; Xilinx Virtexl-4 series SoC; built-in self-test; configurable system-on-chips; embedded FPGA core; embedded memory blocks testing; Automatic testing; Built-in self-test; Field programmable gate arrays; Hardware design languages; Logic testing; Microelectronics; Random access memory; System testing; System-on-a-chip; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Testing and Diagnosis, 2009. ICTD 2009. IEEE Circuits and Systems International Conference on

Conference_Location

Chengdu

Print_ISBN

978-1-4244-2587-7

Type

conf

DOI

10.1109/CAS-ICTD.2009.4960791

Filename

4960791