Design for Low Power Testing of Computation Modules with Contiguous Subspace in VLSI

In this paper, a kind of pseudo Gray code presentation of test patterns based on accumulation generators is presented and a low power test scheme is proposed to test computational function modules with contiguous subspace in VLSI, especially in DSP. If test patterns from accumulators for the modules are encoded in the pseudo Gray code presentation, the switching activities of the modules are reduced, and the decrease of the test power consumption is resulted in. Results of experimentation based on FPGA show that the test approach can reduce dynamic power consumption by an average of 17.40% for 8-bit ripple carry adder consisting of 3-2 counters. Then implementation of the low power test in hardware is exploited. Reused of adders, introduction of additional XOR logic gates is avoided successfully. The design minimums additional hardware overhead for test and need no adjust of circuit structure. The low power test can detect any combinational stuck-at fault within the basic building block without any degradation of original circuit performance.