Title :
A 1.8 V 10-bit 80 MS/s low power track-and-hold circuit in a 0.18 μm CMOS process
Abstract :
A 10-bit low power track-and-hold (T/H) circuit aimed at the front-end of a pipelined analog-to-digital (A/D) converter has been designed. The T/H is sampling at 80 MS/s, has a 30 MHz analog bandwidth and is designed in a 0.18 μm CMOS process with a supply voltage of 1.8 V. A switched capacitor topology incorporating correlated double sampling is used for the T/H circuit and the amplifier is a folded cascode operational transconductance amplifier (OTA) with gain boosting. In this paper, the design of the complete T/H is described, including the derivation of the specifications as well as a straightforward approach for designing the transmission gate switches.
Keywords :
CMOS analogue integrated circuits; analogue-digital conversion; circuit simulation; integrated circuit design; low-power electronics; operational amplifiers; sample and hold circuits; switched capacitor networks; 0.18 micron; 1.8 V; 10 bit; 30 MHz; A/D converter; CMOS process; T/H circuit; amplifier gain boosting; analog bandwidth; analog-to-digital converter; correlated double sampling; folded cascode OTA; low power track-and-hold circuit; operational transconductance amplifier; pipelined ADC front end; sampling rate; switched capacitor topology; transmission gate switches; Analog-digital conversion; Bandwidth; CMOS process; Circuit topology; Operational amplifiers; Sampling methods; Switched capacitor circuits; Switching circuits; Transconductance; Voltage;
Conference_Titel :
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN :
0-7803-7761-3
DOI :
10.1109/ISCAS.2003.1205498
