A resonant pad for ESD protected narrowband CMOS RF applications

As CMOS applications move into the 5.6 GHz UNII band and approach the 10 GHz X-band, the opposing cost and performance design criteria collide. CMOS is extremely susceptible to damage from electro-static discharge (ESD) because CMOS devices are inherently capacitive. Unfortunately, the ESD structure typically used to protect CMOS integrated circuits contributes substantial parasitic capacitance to an RF signal path and is a major impediment to performance. The ESD protection circuitry adversely affects the performance of the low noise amplifier (LNA), often the most critical component in an RF CMOS receiver chain. This paper considers the novel approach of placing a second bond wire acting as an inductor in parallel with the parasitic capacitance of the ESD structure to effectively tune it out. All of the important parasitic effects are modeled and a procedure to incorporate them into the design of a resonating pad is described. Results from simulations using SpectreRF (a Cadence Design Systems simulation tool) show marked improvement in the LNA performance when using the resonating pad compared to conventional pad/ESD designs.